In conventional memory configurations, each data bit in a DRAM cell is stored in a capacitor. Due to leakage, such capacitors leak charge over a period of time. Periodic refreshes are used to charge the capacitors and to restore the data. In a typical 512 Mb double data rate (DDR) memory with 8192 rows, an AUTO REFRESH command is issued every 7.8 us. With such timing, each row is refreshed at least once every 64 ms. The refresh generation logic is a part of the memory controller that issues refresh cycles to the SDRAM once every refresh timing interval (trfi).
It would be desirable to implement a protocol engine that suspends SDRAM refresh cycles during normal DDR operation.